搜索资源列表
H.264_VHDL
- VHDL语言实现H.264的opencore，内涵说明文档、源码和文献等资料。
Verilog-HDL-intra_prediction
- 基于H.264的帧内预测中4×4块的9种预测方法的源程序-H.264 intra prediction based on 4 × 4 block prediction method of the source 9
PlayDemo
- VC写的h.264规范解码程序，具体看程序注释-VC norms h.264 decoding written procedures, specific procedures see Notes
h264coretransform
- it is a vhdl program for core transform in h.264
H264
- H.264的开源代码，绝对权威，代码很大。-H264 vhdl
AnEfficientDouble-FilterHardwareArchitectureforH.2
- 在此提出了一種新穎的硬體結構 實時執行的自適應去塊效應 過濾過程中指定的H.264/AVC視頻編碼 標準。-In this paper,a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented.The deb
DSP_h264_VariableBlockSize
- 這是用verilog HDL實現H.264可變block大小的源碼。為了使其能在FPGA上運作，還加入了我自己的改善。-A verilog HDL code for H.264 with variable block size and my own improvement.
mc
- 通过VHDL实现H.264算法中的半像素插值模块。该模块儿可在30个周期内完成一个4x4块的横纵斜插值。-H.264 algorithm by VHDL implementation of the half pixel interpolation module. The module can be in 30 children complete a cycle of vertical and horizontal 4x4 block Xiecha value.
Cabad
- MPEG-4/AVC - H.264 CABAC decoder written in VHDL and synthesis on a Virtex 5
h264header
- VHDL file for h.264 header
h264invtransform
- H.264 inverse transform in VHDL
h264quantise
- H.264 quantization block in VHDL.
hardh264-src.tar
- VhDl code for low-power design of h.264 system architecture
bb74300fc549
- vhdl code low-power design of h.264 system architecture
h.264
- 包含h.264的包括帧内、帧间、变换编码、熵编码的vhdl源程序-Contains the vhdl source h.264 frame, frame, transform coding, entropy coding
hardh264
- H.264的VHDL描述，可直接在FPGA上仿真运行，也可供学习用-VHDL descr iption of H.264. It can be run on FPGA, and also can be used for study
A-UNIFIED-TRANSFORM-ARCHITECTURE-FOR-H.264-VIDEO-
- A UNIFIED TRANSFORM ARCHITECTURE FOR H.264 VIDEO CODEC VHDL IMPLEMENTATION
Henson
- h.264 vhdl code its the vhdl code of Video compression formats Lossless data compression algorithms
CAVLE-h264
- 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块（Verilog和VHDL两个版本），包含有仿真的testbench测试文件，综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used d
context_modeler_project_1
- VHDL CODE OF context modeler part CABAC (context adaptive binary arithmetic coder) in H.264-VHDL CODE OF context modeler part CABAC (context adaptive binary arithmetic coder) in H.264